With the development of CMOS (complementary metal oxide semiconductor) process and the continuous downscaling of CMOS devices, stress engineering has been playing a more and more importance role in semiconductor processes and device performance. Introduction of stress into CMOS devices is mainly for carrier mobility enhancement, but different types of stresses will have different effects on carrier mobility of the device.
Specifically, a compressive liner will enhance the hole mobility of PMOS devices and thus will significantly improve performance thereof, whilst a tensile liner will reduce the hole mobility of PMOS devices and thus will degrade performance thereof. Similarly, a tensile liner will enhance the electron mobility of NMOS devices and thus will significantly improve performance thereof, whilst a compressive liner will reduce the electron mobility of NMOS devices and thus will degrade performance thereof.
Contact etch stop layer (CESL) process is a stress introduction practice commonly used in the CMOS process. Traditional CESL process is capable of forming a tensile liner to cover the NMOS devices and a compressive liner to cover the PMOS devices to improve the electron and hole mobility therein, respectively, and thus capable of enhancing the performance of NMOS and PMOS devices.
Nevertheless, this CESL process has an extremely high complexity. Moreover, additional compressive stress is not needed in 65 nm PMOS devices and their performance can be ensured if there is no degradation in compressive stress.
In the first-generation CESL process, generally only silicon nitride films providing tensile stress were utilized. As indicated above, because NMOS and PMOS devices need opposite types of stress for performance improvement, beneficial effects of such stress generation films for NMOS devices were always accompanied with disadvantageous effects on the performance of PMOS devices.
Thus, there is a need for a method of effectively improving PMOS performance in the CESL process.